The EDGE-ME project at the University of Siena’s Computer Architecture Laboratory

 

The University of Siena’s Computer Architecture Laboratory, in collaboration with the Italian Center for Supercomputing, is at the forefront of cutting-edge research with the innovative EDGE-ME project, winner of a cascade call in the PNRR area.

“This ambitious initiative – says Professor Roberto Giorgi (Department of Infomation engeneering and Mathematics), coordinator of the project for the University of Siena – is revolutionizing how we approach programming methodologies and tools for complex applications across various hardware platforms that use shared or distributed memory architectures”.

What the project consists of?
“EDGE-ME aims to seamlessly integrate the FastFlow parallel programming model with the DataFlow-Threads (DF-Threads) execution paradigm” – Giorgi explains. “This combination is designed to achieve high-performance and energy-efficient computing on heterogeneous platforms, including FPGAs. The research focuses on developing open-source tools that bridge parallel programming paradigms with the DF-Threads execution model, significantly enhancing the efficiency of application development on diverse architectures”.

  Innovative Programming Models, Open-Source Tools, Real-World Applications, High-Level and Low-Level Integration, Edge Computing Enhancements: specifically, what will the research team work on?
“We combine the FastFlow parallel programming model with the DataFlow-Threads (DF- Threads) execution paradigm to achieve high-performance, energy-efficient computing. This is particularly exciting for applications on heterogeneous platforms, including FPGAs (Field- Programmable Gate Arrays)” – Giorgi explains. “Our team – continues – is dedicated to developing open-source tools that bridge parallel programming paradigms with DF-Threads execution. This makes application development on diverse architectures more efficient and accessible”. “Furthermore – Giorgi adds – we study how to seamlessly integrate high-level programming models with low-level execution mechanisms. This holistic approach enhances the efficiency and scalability of software systems”. “Additionaly we extend the FastFlow framework by incorporating Edge infrastructure management tools like Stack4Things. This integration promises to revolutionize the High-Performance Computing (HPC) ecosystem”.

What about industrial partners?
“Collaborating with SmartMe.io, home of the famous Arancino boards, we evaluate our applications across various domains. This real-world testing ensures our solutions are practical and impactful”. “As the application demand for more performance is increasing more and more – Giorgi continues – in particular with the sophisticated Artificial Intelligence based computation, key objective of the project is to design systems that are sustainable from an energy-savings point of view, while delivering the required performance”.

The project leverages significant hardware advancements, including the High-Bandwidth Memory (HBM) of the Alveo U280 Xilinx board and various other FPGA boards. This is built on the foundation of the FPGA carrier board realized at the University of Siena, known as GLUON, and the full open-source stack developed in the AXIOM project. These technologies provide a robust starting basis for the software, ensuring high efficiency and performance.
“The result – Giorgi points out – is a robust framework that supports scalable, extensible, and reliable parallel applications on edge computing platforms. This advancement is poised to drive significant progress in research and the broader adoption of parallel computing within the scientific and industrial communities. The work being done at the University of Siena, in collaboration with the Italian Center for Supercomputing, is not only pushing the boundaries of current computing capabilities but also setting the stage for future innovations in HPC and beyond for a more sustainable world”.

The project will also rely on an open-source architecture which aims at replacing any new microprocessor: the RISC-V architecture. The University of Siena, in the group lead by prof. Giorgi, has recently joined the RISC-V foundation as a community member.